Ion-implanted junction field effect transistors (hearinafter termed I.sup.2 JFETs) typically contain a buried (ion-implanted) channel region which bridges or joins respective source and drain regions of the JFET and the conductive properties of which are controlled by modulation of the space-charge region width formed with the adjoining top gate and bottom gate regions. The device structure of an exemplary P-channel I.sup.2 JFET is diagrammatically shown in cross-section in FIG. 1 as comprising a substrate (e.g. silicon, gallium arsenide) 10 of N-type conductivity, forming the bottom gate of the device, into a top surface 11 of which respective P-type drain and source regions 15 and 16 are respectively formed. Respective drain and source contact regions 17 and 18 of high impurity concentration P+material are introduced into the surface 11 to a prescribed depth in the respective source and drain regions 15 and 16. Overlying the top surface 11 of the substrate 10 is a field oxide layer 25, a relatively thin portion 14 of which lies atop that portion of the substrate into which a top gate region and channel are to be formed. This is shown diagrammatically in FIG. 1 as being disposed between the respective drain and source regions 15 and 16. Apertures in the field oxide 25 are provided for contacting respective drain and source metallizations 23 and 24 to high impurity concentration P+regions 17 and 18.
The gate/channel structure of the JFET is provided by way of an implanted top gate region 22 of N-type conductivity. Gate region 22 may be formed by implanting suitable N-type conductivity ions, region 22 forming a PN junction 31 with the implanted P material of a channel region 21 provided therebeneath and bridging drain region 15 with source region 16. Channel region 21 forms a PN junction 32 with the N material of the substrate therebeneath. That portion of top gate region 22 which defines a gate-drain PN junction with the P material of drain region 15 is referenced as PN junction 41, an extension of PN junction 31. Also, that portion of top gate region 22 which defines a gate-source PN junction with the P material of source region 16 is referenced as PN junction 42, an extension of PN junction 31.
In operation, the channel region 21 is normally conductive, so as to provide a current path between the drain and source regions 15 and 16. In response to the application of a reverse-biasing gate voltage to the top gate 22 and bottom gate (substrate 10), majority charge carriers are depleted from the channel 21. As the space-charge regions extend into the channel, the channel resistance increases, thereby reducing the current between the drain and the source. The top gate is typically tied to the bottom gate with a suitable high impurity concentration (N+) diffused region (not shown).
In the course of manufacture of the device shown in FIG. 1, the high impurity concentration of the top gate region that is necessary to provide charge carrier supply and thereby prevent the top gate from fully depleting at pinch-off limits the breakdown voltage of the gate-drain PN junction 41 to a value on the order of 10 to 40 volts. In order to increase the breakdown voltage, the concentration gradient of the top gate-drain junction 41 must be decreased. One way of accomplishing this decrease would be to increase the sheet resistance of drain region 15. Unfortunately, this would introduce a separate set of problems.
More particularly, it is typically the case that the P-channel JFET shown in FIG. 1 is integrated with other circuit components, including bipolar devices. As such, the diffusion which forms drain region 15 also forms the P-base of the NPN transistors in the circuit, and must have its sheet resistance optimized for performance of the NPN bipolar transistor. To add a separate diffusion for the drain and source of the JFET in order to modify the concentration gradient of the top gate-drain junction 41 would add an undesirable amount of complexity to the device fabrication process.